Computer Organization & Architecture

Lightweight Dynamic
Branch Prediction

Control Hazard Detection & 5-Stage RISC-V Pipeline Analysis

5-Stage Pipeline
1-bit & 2-bit Predictors
Control Hazards
RISC-V Assembly Editor

Paste or type your code below

beq · bne · blt · bge · jal · jalr · lw · sw · add · sub · addi...
READY
Control Hazard Analysis
0 HAZARDS

No control hazards detected.
Load sample code or write your own.

5-Stage Pipeline Simulator

Branch outcome resolved at EX stage — earlier instructions may be flushed

IF
ID
EX
MEM
WB
Fetch
Decode
Execute
Memory
Writeback
DATA FLOW →
Why This Matters
1
Control Hazard
Branch outcome known only at EX stage. Subsequent IF/ID instructions must be flushed — wasting cycles.
2
Dynamic Prediction
1-bit flips on every mispredict. 2-bit uses saturating counter — more stable in loop-heavy code.
Instruction Breakdown
Total Instructions
0
Arithmetic 0
Memory 0
Branch / Jump 0
Branch Prediction Simulator
Potential Hazards
0
in current code
Each = potential pipeline flush
IF › ID › EX › MEM › WB
v2025.03 • DEMO